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NCV4299 150 mA Low-Dropout Voltage Regulator
The NCV4299 is a family of precision micropower voltage regulators with an output current capability of 150 mA. It is available in 5.0 V or 3.3 V output voltage, and is housed in an 8-lead SON and in a 14-lead SON (fused) package. The output voltage is accurate within "2% with a maximum dropout voltage of 0.5 V at 100 mA. Low Quiescent current is a feature drawing only 90 mA with a 1 mA load. This part is ideal for any and all battery operated microprocessor equipment. The device features microprocessor interfaces including an adjustable reset output and adjustable system monitor to provide shutdown early warning. An inhibit function is available on the 14-lead part. With inhibit active, the regulator turns off and the device consumes less than 1.0 mA of quiescent current. The part can withstand load dump transients making it suitable for use in automotive environments.
Features http://onsemi.com MARKING DIAGRAMS
8 8 1 SO-8 D SUFFIX CASE 751 1 4299 ALYW G
14 NCV4299G AWLYWW 14 1 SO-14 1 D SUFFIX CASE 751A 14 V4299xxG AWLYWW 1 xx = 33 (3.3 V Version) = 50 (5.0 V Version) A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
* 5.0 V, 3.3 V "2%, 150 mA * Extremely Low Current Consumption
* * * * *
* * * *
90 mA (Typ) in the ON Mode t1.0 mA in the Off Mode Early Warning Reset Output Low Down to VQ = 1.0 V Adjustable Reset Threshold Wide Temperature Range Fault Protection 60 V Peak Transient Voltage -40 V Reverse Voltage Short Circuit Thermal Overload Internally Fused Leads in the SO-14 Package Inhibit Function with mA Current Consumption in the Off Mode NCV Prefix for Automotive and Other Applications Requiring Site and Change Control Pb-Free Packages are Available
PIN CONNECTIONS
I SI RADJ D 1 RADJ D GND GND GND INH RO 14 SI I GND GND GND Q SO 1 8 Q SO RO GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
April, 2006 - Rev. 16
Publication Order Number: NCV4299/D
NCV4299
I Q
Bandgap Reference
- +
Current Limit and Saturation Sense RSO
RRO
SO 1.36 V SI + - 8 mA RO - +
RADJ
+ + -
1.85 V
D
GND
Figure 1. SO-8 Simplified Block Diagram
PIN FUNCTION DESCRIPTION - SO-8 PACKAGE
Pin 1 2 3 4 5 6 7 8 Symbol I SI RADJ D GND RO SO Q Description Input. Battery Supply Input Voltage. Bypass directly to GND with ceramic capacitor. Sense Input. Can provide an early warning signal of an impending reset condition when used with SO. Connect to Q if not used. Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used. Reset Delay. Connect external capacitor to ground to set delay time. Ground. Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condition. Leave open if not used. Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning of an impending reset condition. Leave open if not used. 5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 5.0 W to ground.
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NCV4299
I Q
Bandgap Reference
- +
Current Limit and Saturation Sense RSO
RRO INH
SO 1.36 V SI + - 8 mA RO - +
RADJ
+ + -
1.85 V
D
GND
Figure 2. SO-14 Simplified Block Diagram
PIN FUNCTION DESCRIPTION - SO-14 PACKAGE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol RADJ D GND GND GND INH RO SO Q GND GND GND I SI Description Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used. Reset Delay. Connect external capacitor to ground to set delay time. Ground. Ground. Ground. Inhibit. Connect to I if not needed. A high turns the regulator on. Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condition. Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning of an impending reset condition. 5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 5.0 W to ground. Ground. Ground. Ground. Input. Battery Supply Input Voltage. Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
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NCV4299
MAXIMUM RATINGS
Rating Input Voltage to Regulator (DC) Input Peak Transient Voltage to Regulator wrt GND Inhibit (INH) (Note 1) Sense Input (SI) Sense Input (SI) Reset Threshold (RADJ) Reset Threshold (RADJ) Reset Delay (D) Reset Output (RO) Sense Output (SO) Output (Q) Output (Q) ESD Capability, Human Body Model (Note 5) ESD Capability, Machine Model (Note 5) ESD Capability, Charged Device Model (Note 5) Junction Temperature Storage Temperature Symbol VI - VINH VSI ISI VRE IRE VD VRO VSO VQ IQ ESDHB ESDMM ESDCDM TJ Tstg Min -40 - -40 -0.3 -1.0 -0.3 -10 -0.3 -0.3 -0.3 -0.3 -5.0 2.0 200 1.0 - -50 Max 45 60 45 45 1.0 7.0 10 7.0 7.0 7.0 16 - - - - 150 150 Unit V V V V mA V mA V V V V mA kV V kV C C
OPERATING RANGE
Input Voltage 5.0 V Version 3.3 V Version Junction Temperature VI 4.5 4.4 TJ -40 45 45 150 C V
LEAD TEMPERATURE SOLDERING REFLOW (Note 3)
Lead Temperature Soldering (Note 5) Reflow (SMD styles only), leaded 60-150 sec above 183, 30 sec max at peak Reflow (SMD styles only), lead free 60s-150 sec above 217, 40 sec max at peak Moisture Sensitivity Level TSLD - TSLD - MSL Level 1 265 Pk 240 Pk C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 14 pin package only. 2. Preliminary numbers. 3. Per IPC / JEDEC J-STD-020C. 4. Measured to Pin 4. All ground pins connected to ground. 5. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC-Q100-002 (EIA/JESD22-A114) ESD MM tested per AEC-Q100-003 (EIA/JESD22-A115) ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model.
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NCV4299
THERMAL CHARACTERISTICS
Characteristic Test Conditions (Typical Value) Note 6 SO-8 Junction-to-Tab (yJLx, qJLx) Junction-to-Ambient (RJA, qJA) Junction-to-Tab (yJLx, qJLx) Junction-to-Ambient (RJA, qJA) 54 172 19 112 Note 7 52 144 21 89 Note 8 C/W 48 118 C/W 20 67 Unit
SO-14
6. 2 oz Copper, 50 mm sq Copper area, 1.5 mm thick FR4 7. 2 oz Copper, 150 mm sq Copper area, 1.5 mm thick FR4 8. 2 oz Copper, 500 mm sq Copper area, 1.5 mm thick FR4
ELECTRICAL CHARACTERISTICS (-40C < TJ < 150C; VI = 13.5 V unless otherwise noted.)
Characteristic Output Q Output Voltage (5.0 V Version) Output Voltage (3.3 V Version) Current Limit Quiescent Current (Iq = II - IQ) Quiescent Current (Iq = II - IQ) Quiescent Current (Iq = II - IQ) Quiescent Current (Iq = II - IQ) Quiescent Current (Iq = II - IQ) Dropout Voltage (Note 9) Load Regulation Line Regulation Power Supply Ripple Rejection Inhibit (INH) (14 Pin Package Only) Inhibit Off Voltage Inhibit On Voltage 5.0 V Version 3.3 V Version Input Current VINHOFF VINHON VQ > 4.85 V VQ > 3.2 V IINHON IINHOFF INH ON INH = 0 V 3.5 3.5 - - - - 3.0 0.5 - - 10 2.0 mA VQ < 1.0 V - - 0.8 V V VQ VQ IQ Iq Iq Iq Iq Iq Vdr DVQ DVQ PSRR 1.0 mA < IQ < 150 mA, 6.0 V < VI < 16 V 1.0 mA < IQ < 150 mA, 5.5 V < VI < 16 V - INH ON, IQ < 1.0 mA, TJ = 25C INH ON, IQ < 1.0 mA INH ON, IQ = 10 mA INH ON, IQ = 50 mA INH = 0 V, TJ = 25C IQ = 100 mA IQ = 1.0 mA to 100 mA VI = 6.0 V to 28 V, IQ = 1.0 mA r = 100 Hz, Vr = 1.0 Vpp, IQ = 100 mA 4.9 3.23 250 - - - - - - - - - 5.0 3.3 400 86 90 170 0.7 - 0.22 5.0 10 66 5.1 3.37 500 100 105 500 2.0 1.0 0.50 30 25 - V V mA mA mA mA mA mA V mV mV dB Symbol Test Conditions Min Typ Max Unit
Reset (RO) Switching Threshold 5.0 V Version 3.3 V Version Output Resistance Reset Output Low Voltage 5.0 V Version 3.3 V Version Allowable External Reset Pullup Resistor Delay Upper Threshold Delay Lower Threshold Vrt - 4.50 2.96 RRO VRO Q < 4.5 V, Internal RRO, IRO = -1.0 mA Q < 2.96 V, Internal RRO, IRO = -1.0 mA VROext VUD VLD External Resistor to Q - - - - 5.6 1.5 0.4 0.17 0.17 - 1.85 0.5 0.40 0.40 - 2.2 0.6 kW V V - 10 4.60 3.06 20 4.80 3.16 40 kW V V
9. Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
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NCV4299
ELECTRICAL CHARACTERISTICS (continued) (-40C < TJ < 150C; VI = 13.5 V unless otherwise noted.)
Characteristic Reset (RO) Delay Output Low Voltage 5.0 V Version 3.3 V Version Delay Charge Current 5.0 V Version 3.3 V Version Power On Reset Delay Time Reset Reaction Time Reset Adjust Switching Threshold 5.0 V Version 3.3 V Version Input Voltage Sense (SI and SO) Sense Input Threshold High Sense Input Threshold Low Sense Input Hysteresis VSI,HIGH VSI,LOW - - - (Sense Threshold High) - (Sense Threshold Low) - - VSI < 1.20 V, VI > 4.2 V, ISO = 0 mA - - - 1.34 1.26 50 1.45 1.36 90 1.54 1.44 130 V V mV mA kW V kW ms ms VD Q < 4.5 V, Internal RRO Q < 2.96 V, Internal RRO ID Q < 4.5 V, Internal RRO, VD = 1.0 V Q < 2.96 V, Internal RRO, VD = 1.0 V td trr VRADJ,TH Q > 3.5 V Q > 2.3 V 1.26 - 1.36 - 1.44 - CD = 100 nF CD = 100 nF 4.0 - 17 0.5 7.1 - 28 2.2 12 - 35 4.0 ms ms V - - - 0.017 0.1 0.1 mA V Symbol Test Conditions Min Typ Max Unit
Sense Input Current Sense Output Resistance Sense Output Low Voltage Allowable External Sense Out Pullup Resistor SI High to SO High Reaction Time SI Low to SO Low Reaction Time
ISI RSO VSO RSOext tpdSOLH tpdSOHL
-1.0 10 - 5.6 - -
0.1 20 0.1 - 4.4 3.8
1.0 40 0.4 - 8.0 5.0
II VI I Q
IQ VQ
VINH
IINH (14-Pin Part Only) CD 100 nF IRADJ ISI ID
INH D NCV4299
RO
ID
VRO
VRADJ VSI
RADJ SI GND SO
VSO
Iq
Figure 3. Measurement Circuit
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NCV4299
TYPICAL PERFORMANCE CHARACTERISTICS - 5.0 V OPTION
5.1 OUTPUT VOLTAGE, VQ VOLTS VI = 13.5 V RL = 1 kW VQ VOLTS 6 5 4 3 2 1 RL = 50 W 0 20 40 60 80 100 120 140 160 TEMPERATURE C 0 0 5 10 INPUT VOLTAGE, VI VOLTS 15
5.0
4.9 -40 -20
Figure 4. Output Voltage VQ vs. Temperature TJ
Figure 5. Output Voltage VQ vs. Input Voltage
8.0 DROP VOLTAGE, Vdr, mV CHARGE CURRENT, mA VI = 13.5 V VD = 1 V RL = 5 kW
500 125C 25C 300 -40C
400
7.0
200
100
6.0 -40 -20
0 0 20 40 60 80 100 120 140 160 TEMPERATURE C 0 50 100 OUTPUT CURRENT IQ, mA 150
Figure 6. Charge Current ld, c vs. Temperature TJ
Figure 7. Drop Voltage Vdr vs. Output Current IQ
3.2 2.8 SWITCHING VOLTAGE, V
1.5 1.4
2.4 2.0 1.6 1.2 0.8 0.4 0.0 -40 0 40 80 TEMPERATURE, C 120 160 VLD, VI = 13.5V 1.0 0.9 -40 VRADJTH, V VUD 1.3 1.2 1.1
0
40 80 TEMPERATURE TJ, C
120
160
Figure 8. Switching Voltage VUD and VLD vs. Temperature TJ
Figure 9. Reset Adjust Switching Threshold VRADJTH vs. Temperature TJ
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NCV4299
1.6 1.5 1.4 VSI, V 1.3 1.2 1.1 1.0 -40 VSIU VSIL OUTPUT CURRENT IQ, mA 350 300 TJ = 25C 250 TJ = 125C 200 150 100 50 VQ = 0 V 0 40 80 TEMPERATURE, C 120 160 0 0 10 20 30 INPUT VOLTAGE, VI, V 40
Figure 10. Sense Threshold VSI vs. Temperature TJ
Figure 11. Output Current Limit IQ vs. Input Voltage, VI
CURRENT CONSUMPTION Iq, mA
CURRENT CONSUMPTION Iq, mA 0 30 20 40 OUTPUT CURRENT IQ, mA 50 60
2.0
8.0
1.5
6.0
1.0
4.0
0.5
2.0
0.0
10
0.0
0
40 120 80 OUTPUT CURRENT IQ, mA
160
Figure 12. Current Consumption Iq vs. Output Current IQ
Figure 13. Current Consumption Iq vs. Output Current IQ
40 RRO, RSO RESISTANCE, Ohms VI = 13.5V RL = 5 kW 30 CURRENT CONSUMPTION Iq, mA
16.0 14.0 12.0 10.0 RL 200W RL 100W 8.0 6.0 4.0 2.0 0.0 0 10 20 30 INPUT VOLTAGE VI, V 40 RL 50W RL 33W
20
10 -40
0
40 80 TEMPERATURE C
120
160
Figure 14. RRO, RSO Resistance vs. Temperature
Figure 15. Current Consumption Iq vs. Input Voltage VI
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NCV4299
90 85 80 75 70 65 60 6 8 10 12 14 16 18 20 INPUT VOLTAGE VI, V 22 24 26 CURRENT CONSUMPTION Iq, mA CURRENT CONSUMPTION Iq, mA 6 5 IQ 50mA 4 3 IQ 10mA 2 1 0 6 8 10 12 14 16 18 20 INPUT VOLTAGE VI, V 22 24 26
IQ 100 mA
IQ 100mA
Figure 16. Current Consumption Iq vs. Input Voltage VI
Figure 17. Current Consumption Iq vs. Input Voltage VI
45 OUTPUT CAPACITOR ESR, Ohms 40 35 30 25 20 15 10 5 0 0 20 40 60 80 100 120 OUTPUT CURRENT, mA 140 160 Stable Region Unstable Region 0.1 mF Only 1 mF to 100 mF 0.1 mF Unstable Region VI = 13.5V TA = 25C
Figure 18. Stability vs. Output Capacitor ESR
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NCV4299
TYPICAL PERFORMANCE CHARACTERISTICS - 3.3 V OPTION
1000 IQ, CURRENT CONSUMPTION (mA) VI = 13.5 V 100 IQ = 1 mA 10 12 10 8 6 4 2 0 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 180 TJ, JUNCTION TEMPERATURE (C) IQ, OUTPUT CURRENT (mA) TJ = 150C TJ = 25C TJ = -40C
1
0.1 -40 -20
Figure 19. Current Consumption vs. Junction Temperature
IQ, CURRENT CONSUMPTION (mA) 5 TJ = 25C 4 VQ, OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 -40 3.5
IQ, CURRENT CONSUMPTION (mA)
Figure 20. Current Consumption vs. Output Current
VI = 13.5V RL = 1 kW
3 RL = 33 W 2 RL = 50 W 1 0 0 10 20 30 40 VI, INPUT VOLTAGE (V) RL = 100 W 200 50
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (C)
Figure 21. Current Consumption vs. Input Voltage
IQ, MAXIMUM OUTPUT CURRENT (mA) IQ, REVERSE OUTPUT CURRENT (mA) 0 VI = 0 V -50 TJ = 125C 350 300 250 200 150 100 50 0 0
Figure 22. Output Voltage vs. Junction Temperature
TJ = 25C TJ = 125C
-100 -150 TJ = 25C TJ = -40C -200 -250 -300 0 10 20 30 40 50 VQ, OUTPUT VOLTAGE (V)
VQ = 0 V 25 VI, INPUT VOLTAGE (V) 50
Figure 23. Reverse Output Current vs. Output Voltage
Figure 24. Maximum Output Current vs. Input Voltage
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NCV4299
6 5 RL = 50 W 4 3 2 1 0 0 1 2 3 4 5 VI, INPUT VOLTAGE (V) OUTPUT CAPACITOR ESR (W) TJ = 25C VQ, OUTPUT VOLTAGE (V) 1000
100
Max ESR for Vin = 6 V Max ESR for Vin = 25 V
10
1
Stable Region
0.1 0.01 0
CQ = 22 mF TJ = 150C 10 40 70 100 130
IQ, OUTPUT CURRENT (mA)
Figure 25. Output Voltage at Input Voltage Extremes
1000 IINH, INHIBIT INPUT CURRENT (mA) OUTPUT CAPACITOR ESR (W) 0.02
Figure 26. 3.3 V Output Stability with Output Capacitor ESR
INH = OFF 0.01 TJ = -40C 0 -0.01 -0.02 -0.03 -0.04 -0.05 0 10 20 30 TJ = 150C 40 TJ = 25C TJ = 125C
100
Max ESR for Vin = 6 V Max ESR for Vin = 25 V
10
1 Stable Region 0.1 0.01 0 CQ = 22 mF TJ = -40C 10 40 70 100 130
IQ, OUTPUT CURRENT (mA)
VI, INPUT VOLTAGE (V)
Figure 27. 3.3 V Output Stability with Output Capacitor ESR
6 IINH, INHIBIT INPUT CURRENT (mA) 5 4 TJ = 125C 3 2 1 0 0 10 20 30 40 VINH, INHIBIT INPUT VOLTAGE (V) TJ = -40C TJ = 25C VRT, RESET TRIGGER THRESHOLD (V) 3.25
Figure 28. Inhibit Input Current at Input Voltage Extremes
VI = 13.5 V 3.20 3.15 3.10 3.05 3.00 2.95 -40 -20 Reset
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (C)
Figure 29. Inhibit Input Current at Inhibit Input Voltage Extremes
Figure 30. Reset Trigger Threshold vs. Junction Temperature
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NCV4299
35 TRD, RESET DELAY TIME (ms) VSI, SENSE THRESHOLD (V) VI = 13.5 V CD = 100 nF 1.50 VI = 13.5 V 1.45 VSI High
30
25
1.40
20
15 10 -40 -20
1.35
VSI Low
0
20
40
60
80
100 120 140
1.30 -40 -20
0
20
40
60
80
100 120 140
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 31. Reset Delay Time vs. Junction Temperature
8 ICH, DELAY CAPACITOR CHARGE CURRENT (mA) 7 VDR, DROP VOLTAGE (V) 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 VI = 13.5 V VD = 1 V 100 120 140 1.15 1.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 0
Figure 32. Sense Threshold vs. Junction Temperature
TJ = 125C
TJ = -40C TJ = 25C
VDR = VImin - VQ 40 80 120 160
TJ, JUNCTION TEMPERATURE (C)
IQ, OUTPUT CURRENT (mA)
Figure 33. Delay Capacitor Charge Current vs. Junction Temperature
VUD, VLD, SWITCHING VOLTAGE (V) 3.0 VI = 13.5 V 2.5 2.0 1.5 1.0 VLD 0.5 0 -40 1.0 0.9 -40 VUD 1.4 1.3 VRADJ,th (V) 1.2 1.1 1.5
Figure 34. Drop Voltage vs. Output Current
0
40
80
120
160
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 35. Switching Voltage VUD and VLD vs. Junction Temperature
Figure 36. Reset Adjust Switching Threshold vs. Junction Temperature
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1.5 RRO, RSO RESISTANCE (kW) TJ = 25C 40 35 30 25 20 15 10 -40
IQ, CURRENT CONSUMPTION (mA)
1.0
0.5 IQ = 10 mA IQ = 1 mA
0 0 10 20 30 40 VI, INPUT VOLTAGE (V)
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (C)
Figure 37. Current Consumption vs. Input Voltage
Figure 38. RRO, RSO Resistance vs. Junction Temperature
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APPLICATION DESCRIPTION
NCV4299
The NCV4299 is a family of precision micropower voltage regulators with an output current capability of 150 mA at 5.0 V and 3.3 V. The output voltage is accurate within "2% with a maximum dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature drawing only 90 mA with a 100 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active reset output RO (with delay), and a SI/SO monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. The use of the SI/SO monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. Internal output resistors on the RO and SO pins pulling up to the output pin Q reduce external component count. An inhibit function is available on the 14-lead part. With inhibit active, the regulator turns off and the device consumes less that 1.0 mA of quiescent current. The active reset circuit operates correctly at an output voltage as low as 1.0 V. The reset function is activated during the powerup sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to the RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments.
NCV4299 Circuit Description
Other features of the regulator include an undervoltage reset function and a sense circuit. The reset function has an adjustable time delay and an adjustable threshold level. The sense circuit trip level is adjustable and can be used as an early warning signal to the controller. An inhibit function that turns off the regulator and reduces the current consumption to less than 1.0 mA is a feature available in the 14 pin package.
Output Regulator
The output is controlled by a precision trimmed reference. The PNP output has saturation control for regulation while the input voltage is low, preventing oversaturation. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits.
Stability Considerations
The low dropout regulator in the NCV4299 uses a PNP pass transistor to give the lowest possible dropout voltage capability. The current is internally monitored to prevent oversaturation of the device and to limit current during over current conditions. Additional circuitry is provided to protect the device during overtemperature operation. The regulator provides an output regulated to 2%.
The input capacitor CI is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 W in series with CI. The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The value for the output capacitor CQ shown in Figures 39 and 40 should work for most applications, however, it is not necessarily the optimized solution. Stability is guaranteed at values CQ w 22 mF and an ESR v 5.0 W within the operating temperature range. Actual limits are shown in a graph in the typical performance characteristics section.
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NCV4299
VBAT CI* 0.1 mF I Q RRADJ1 RADJ RRADJ2 D CD NCV4299 RS11 SI RS12 CQ** 22 mF Microprocessor I/O I/O VDD RRADJ1 RADJ RRADJ2 D CD NCV4299 RS11 SI RS12 INH INH SO GND RO I/O I/O CQ** 22 mF Microprocessor VDD
SO GND
RO
*CI required if regulator is located far from the power supply filter. **CQ required for stability. Cap must operate at minimum temperature expected.
Figure 39. Test and Application Circuit Showing all Compensation and Sense Elements for the 8 Pin Package Part
VBAT CI* 0.1 mF
I
Q
*CI required if regulator is located far from the power supply filter. **CQ required for stability. Cap must operate at minimum temperature expected.
Figure 40. Test and Application Circuit Showing all Compensation and Sense Elements for the 14 Pin Package Part with Inhibit Function
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NCV4299
Reset Output (RO)
A reset signal, Reset Output (RO, low voltage) is generated as the IC powers up. After the output voltage VQ increases above the reset threshold voltage VRT, the delay timer D is started. When the voltage on the delay timer VD passes VUD, the reset signal RO goes high. A discharge of the delay timer (VD) is started when VQ drops and stays below the reset threshold voltage VRT. When the voltage of
VI
the delay timer (VD) drops below the lower threshold voltage VLD, the reset output voltage VRO is brought low to reset the processor. The reset output RO is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC, thereby guaranteeing that RO is valid for VQ as low as 1.0 V.
t < tRR VQ VRT t VD VUD VLD td tRR t dV + ID dt CD
VRO
VRO, SAT t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
Figure 41. Reset Timing Diagram Reset Adjust (RADJ) Reset Delay (D)
The reset threshold VRT can be decreased from a typical value of 4.65 V to as low as 3.5 V by using an external voltage divider connected from the Q lead to the pin RADJ, as shown in Figures 39 and 40. The resistor divider keeps the voltage above the VRADJ,TH, (typ. 1.35 V), for the desired input voltages and overrides the internal threshold detector. Adjust the voltage divider according to the following relationship:
VTHRES + VRADJ, TH * (RADJ1 ) RADJ2) RADJ2
(eq. 1)
If the reset adjust option is not needed, the RADJ-pin should be connected to GND causing the reset threshold to go to its default value (typ. 4.65 V).
The reset delay circuit provides a delay (programmable by capacitor CD) on the reset output RO lead. The delay lead D provides charge current ID (typically 8.0 mA) to the external delay capacitor CD during the following times: 1. During Powerup (once the regulation threshold has been exceeded). 2. After a reset event has occurred and the device is back in regulation. The delay capacitor is set to discharge when the regulation (VRT, reset threshold voltage) has been violated. When the delay capacitor discharges to down to VLD, the reset signal RO pulls low.
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NCV4299
Setting the Delay Time Sense Input (SI)/Sense Output (SO) Voltage Monitor
The delay time is set by the delay capacitor CD and the charge current ID. The time is measured by the delay capacitor voltage charging from the low level of VD,sat to the higher level VUD. The time delay follows the equation:
td + [CD (VUD-VD, sat)] ID
(eq. 2)
Example: Using CD = 100 nF. Use the typical value for VD,sat = 0.1 V. Use the typical value for VUD = 1.8 V. Use the typical value for Delay Charge Current ID = 6.5 mA.
td + [100 nF(1.8-0.1 V)] 6.5 mA + 26.2 ms
(eq. 3)
An on-chip comparator is available to provide early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the SO pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the band gap voltage. The actual trip point can be programmed externally using a resistor divider to the input monitor (SI) (Figures 39 and 40). The typical threshold is 1.35 V on the SI Pin.
Signal Output
When the output voltage VQ drops below the reset threshold voltage VRT, the voltage on the delay capacitor VD starts to drop. The time it takes to drop below the lower threshold voltage of VLD is the reset reaction time, tRR. This time is typically 1.0 ms for a delay capacitor of 0.1 mF. The reset reaction time can be estimated from the following relationship:
tRR + 10 ns nF CD
(eq. 4)
Figure 42 shows the SO Monitor waveforms as a result of the circuits depicted in Figures 39 and 40. As the output voltage VQ falls, the monitor threshold VSI,LOW is crossed. This causes the voltage on the SO output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal.
Sense Input Voltage
VQ
VSL, High
SI VSI,LOW VRO
VSL, Low
Sense Output High
tPD SO LH
t tPD SO HL
SO Low t
TWARNING
Figure 42. SO Warning Timing Waveform Calculating Power Dissipation in a Single Output Linear Regulator
Figure 43. Sense Timing Diagram
The maximum power dissipation for a single output regulator is:
PD(max) + [VI(max)-VQ(min)] IQ(max) ) VI(max)Iq
(eq. 5)
Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
RqJA + (150C-TA) PD
(eq. 6)
where: VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in Equation 6 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
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NCV4299
Heatsinks
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor website.
A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(eq. 7)
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NCV4299
SOIC 8 LEAD
1000 Cu Area = 10 mm2, 1.0 oz 100 R(t) (C/W) 25 mm2, 1.0 oz 100 mm2, 1.0 oz 10 250 mm2, 1.0 oz 500 mm2, 1.0 oz 1
0.1 0.000001 0.00001
0.0001
0.001
0.01 Time (sec)
0.1
1
10
100
1000
Figure 44. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log-Log)
1000 100 10 50% Duty Cycle 20% 10%
R(t) (C/W)
5% 2% 1 1% Single Pulse (SOIC-8)
0.1 0.01
Psi LA (SOIC-8) 0.001 0.000001 0.00001 0.0001 0.001 0.01 Pulse Time (sec) 0.1 1 10 100 1000
Figure 45. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log-Log) (PCB = 50 mm2 1 oz)
1000 100 50% Duty Cycle 20% 10% 10 5% 2% 1 1% 0.1 0.01 Psi LA (SOIC-8) 0.001 0.000001 0.00001 0.0001 0.001 0.01 Pulse Time (sec) 0.1 1 10 100 1000 Single Pulse (SOIC-8)
R(t) (C/W)
Figure 46. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log-Log) (PCB = 250 mm2 1 oz)
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NCV4299
SOIC 14 LEAD
1000 Cu Area = 10 mm2, 1.0 oz 100 R(t) (C/W) 25 mm2, 1.0 oz 10 100 mm2, 1.0 oz 250 mm2, 1.0 oz 1 500 mm2, 1.0 oz
0.1 0.000001 0.00001
0.0001
0.001
0.01 Time (sec)
0.1
1
10
100
1000
Figure 47. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log-Log)
1000 100 50% Duty Cycle 20% 10% 10 5% 2% 1 1% 0.1 Single Pulse (SOIC-14) 0.01 Psi LA (SOIC-14) 0.001 0.000001 0.00001 0.0001 0.001 0.01 Pulse Time (sec) 0.1 1 10 100 1000
R(t) (C/W)
Figure 48. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log-Log) (PCB = 50 mm2 1 oz)
100 50% Duty Cycle 10 20% 10% 5% 1 2% 1% 0.1 Single Pulse (SOIC-14) 0.01 Psi LA (SOIC-14) 0.001 0.000001 0.00001 0.0001 0.001 0.01 Pulse Time (sec) 0.1 1 10 100 1000
R(t) (C/W)
Figure 49. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log-Log) (PCB = 250 mm2 1 oz)
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NCV4299
ORDERING INFORMATION
Device NCV4299D1 NCV4299D1G NCV4299D1R2 NCV4299D1R2G NCV4299D2 NCV4299D2G NCV4299D2R2 NCV4299D2R2G NCV4299D233G NCV4299D233R2G Package SO-8 SO-8 (Pb-Free) SO-8 SO-8 (Pb-Free) SO-14 SO-14 (Pb-Free) SO-14 SO-14 (Pb-Free) SO-14 (Pb-Free) SO-14 (Pb-Free) Shipping 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 55 Units/Rail 55 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCV4299
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV4299
PACKAGE DIMENSIONS
SO-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NCV4299/D

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